This invention relates to integrated-circuit field-effect transistors having floating gates, and more particularly to floating-gate field-effect transistors formed on the vertical walls of trenches formed in layers of doped semiconductor material.
Floating-gate, avalanche-injection, metal-oxide-semiconductor (FAMOS) transistors are commonly used in erasable programmable read-only-memories (EPROMs) and in electrically erasable programmable read-only-memories (EEPROMs). The floating gates of such devices are located between the programming gates and the transistor channels and are separated from the programming gates and from the transistor channels by layers of silicon dioxide or other electrically insulating material. During programming of an EPROM, a large voltage of sufficient positive magnitude is applied to the programming gate to cause negatively charged electrons to be transferred from the source-channel-drain region to the floating gate. The charge on a floating gate of an EPROM may be erased by allowing light or other radiation to enter the floating-gate region. The charge on the floating gate of an EEPROM may be erased by applying a voltage of sufficient negative magnitude to the programming gate to cause the excess electrons in the floating gate to transfer to the source-channel-drain region. In general, prior-art EEPROMs are characterized by configurations that, during programming and erasing, restrict the charge transfer to a particular path between the source-channel-drain region and the floating gate.
EPROMs and EEPROMs are usually formed on planar substrates with the source-channel-drains and gate surfaces having horizontal geometries. Horizontal formation of gates and source-channel-drain regions requires use of a relatively large area on the surface of a microchip for each transistor. As the component density of integrated-circuit memory arrays increases, it is necessary to decrease the area used by each transistor.
In addition, use of horizontal-geometry structures limits the ability of the designer to increase the floating gate-to-channel electric field during programming/erasing while at the same time limiting the magnitude of programming/erasing voltages. In order to limit the programming-gate voltages to reasonably safe values during programming and erasing and at the same time create floating gate-to-channel electric fields of sufficient magnitude to cause tunneling of electric charge, designers of prior-art planar structures have added separate tunneling areas having relatively short dimensions between the floating gate and a part of the source-channel-drain surface.
While the prior art discloses formation of vertical transistors having gate and source-channel-drain surfaces formed on the vertical walls of a trench for the purpose of decreasing the area required for those transistors, no known disclosure includes formation of a floating-gate transistor on a vertical wall of a trench in a manner that increases the floating gate-to-channel electric fields during programming and erasing while at the same time limiting the magnitude of programming-gate voltages applied during programming and erasing to reasonably small values without use of a separate tunneling area.